1. Field of the Invention
This invention relates to phase-locked frequency multiplier systems and methods. More specifically, the invention is a method and system that utilizes processor interrupts to generate an output signal frequency that is a multiple of an input signal's frequency and phase-locked to the input signal.
2. Description of the Related Art
A frequency multiplier is generally used to generate an output signal having a frequency that is a multiple of an input signal's frequency. When the input signal is variable, it may also be necessary to synchronize the output signal to variations in the input signal's frequency and phase. For example, data acquisition systems are frequently synchronized to the periodic occurrence of some event, the frequency of which can vary over time.
Phase-locked loops (or PLLs as they are also known) are well known feedback circuits used to keep an output signal synchronized or locked with respect to variations in the input signal's frequency and phase. Conventional analog or digital PLLs are implemented in hardware. However, this means that circuits must be specially designed and built for different applications. This is wasteful given that many frequency multiplier applications requiring PLLs already have an under-utilized processing system associated therewith.